Intel and Micron team up for smaller, denser flash

Intel is partnering with Micron to launch three bit per cell (3bpc) multi-level cell (MLC) NAND flash by the end of the year.

The companies claimed the chip measures only 126mm square and that its capacity of 32Gb makes it the smallest and most efficient in today's market.

Having three bits per cell increases the density of the flash in a small chip, meaning less room is required for larger storage.

Randy Wilhelm, vice president of Intel's NAND Solutions Group, said in a statement: "The move to 3bpc is yet another proof point to the remarkable progress Intel and Micron have made in 34-nm NAND development."

"This milestone sets the stage for continued silicon leadership on 2xnm process that will help decrease costs and increase the capabilities of our NAND solutions for our customers."

The two firms have developed NAND flash technology together since 2005 but this is the first they have done together using 34nm lithography.

Jennifer Scott is a former freelance journalist and currently political reporter for Sky News. She has a varied writing history, having started her career at Dennis Publishing, working in various roles across its business technology titles, including ITPro. Jennifer has specialised in a number of areas over the years and has produced a wealth of content for ITPro, focusing largely on data storage, networking, cloud computing, and telecommunications.

Most recently Jennifer has turned her skills to the political sphere and broadcast journalism, where she has worked for the BBC as a political reporter, before moving to Sky News.